The present disclosure relates to a program execution device, and more particularly to a technique for reducing a translation look-aside buffer (TLB) miss rate during program execution.
An application accessing a memory space that is enormous in size has increased in popularity in recent years due to the spread of full high definition (Full HD) equipment. In general, an application refers to a TLB for high-speed access to a memory. If a logical address to be accessed by the application is not in the TLB, it is a TLB miss.
If a TLB miss occurs, the application accesses an address conversion table managed by an operating system. Then, a logical address to be accessed and a physical address corresponding to this logical address are registered to a TLB entry from the address conversion table, and thus an overhead occurs. This results in reduction in an execution speed of the application.
FIG. 10 illustrates a conventional address conversion system. A central processing unit (CPU) 3 includes a memory management unit (MMU) 4 including a TLB 5 converting a logical address located in a logical address space 1 into a physical address located in a physical address space 2. Conventionally, a page size of a TLB entry is increased to expand an address range stored in the TLB entry in order to prevent occurrence of a TLB miss (see, e.g., Japanese Patent Publication No. 2000-57054 and Japanese Patent Publication No. 2010-191645).